The past decade has witnessed a remarkable miniaturization of electronic devices with ever increasing complexity and functionality. The move towards enhanced functionality while minimizing circuit size has led electronics designers to incorporate more functionality per integrated circuit (“IC”) as well as integrate the functions previously handled by a group of ICs into a single IC. In either case, a side effect of larger scale integration has been the issue of how to send and extract aggrandizing amounts as well as more varied types of data to and from these super-size chips. The conventional response has been to increase pinout of the chip carrier packages housing such ICs thereby providing more potential connection points to other electronic components and devices, including other ICs. But, once nominal two-dimensional pin density has been achieved in traditional circuit board applications, as in the case of ball grid array and pin grid array packaged ICs, further increasing the number of pins or leads requires a proportionally larger chip package and consequent circuit board real estate to accommodate them. Moreover, additional pins means additional circuit traces and lead lines which increase circuit board layout complexity, opportunities for noise and interference in high-speed and RF applications, and cuts against opportunities for further size reduction.
In another approach, especially useful in price-sensitive consumer applications, the industry has re-embraced the use of commodity or modular integrated circuits which can easily be cobbled together to perform required functionality. This approach avoids having to design a custom integrated circuit and its attendant high development, production and testing costs. However, the market still requires more functionality in a smaller package, electronics designers still must place a premium on board real estate and must make general efforts to reduce or minimize the number of chip traces as well as focus on smaller modular chips having smaller landing areas and consequently more compact or reduced chip carrier pinouts since pinouts are becoming a primary limiting factor in chip carrier minaturization. Accordingly, in either approach there is a need to reduce the number of pins required as well as the number of traces or intercircuit communication lines that need to be accommodated in order to carry out interchip and, more generally, intercircuit communications.
FIG. 1 illustrates a simplified diagram of a circuit board 50 including first and second IC chip carriers or chips 60, 80 disposed thereon. A generic communications path 70 communicatively couples the first and second chips 60, 80 and typically includes one or more signal traces. It would be advantageous to reduce the number of traces within the communications path 70 and ultimately reduce pinout requirements for communicating information between the first and second chips along this path 70.
FIG. 2 illustrates an prior art interchip communication scheme consistent with the board level environment shown in FIG. 1. In particular, this figure illustrates conventional intercircuit communication between an RF-baseband conversion circuit 100 and a baseband processing circuit 150 of a wireless receiver. This wireless receiver may be configured for operation consistent with the base IEEE 802.11 (1999) Standard as well as the high rate PHY extensions IEEE 802.11b (1999), IEEE 802.11a (1999), and/or draft IEEE 802.11g (2002). Thus, the RF circuit includes an RF to IF demodulator 103, a variable gain amplifier (“VGA”) 105, and an IF to baseband downconverter 107 to present the baseband analog signal bearing the received data of interest to the baseband processing circuit 150. The VGA 105 forms an operational part of a self-adjusting or automatic gain control system which spans the ICs 60, 80.
The automatic gain control system seeks to optimize the amplitude of the still phase-modulated analog IF signal 104 generated by the demodulator 103 to ensure that the dynamic range of the analog-to-digital converter (“ADC”) 115 of the baseband processing circuit 150 is fully utilized when converting the baseband version 108 of this signal into digital form. Gain feedback from the output of the ADC 115 or the adjacent bandpass filter or FIR 129 is utilized to automatically compensate and control the variable gain amplifier 105. However, since the feedback is obtained within the second chip 80 and the VGA 105 is formed within the first chip 60 as part of the RF-baseband processing circuit 100, the feedback must be sent across an interposing interchip data path such as the data path 70 shown in FIG. 1. To that end, feedback output of the ADC 115 or the FIR 120 (depending on the implementation) is fed to a gain comparison unit 152 of an automatic gain control (“AGC”) feedback unit 151 for comparison against an ideal or nominal gain signal (“GAIN TARGET” in FIG. 2) as is well known in the art. The instaneous gain error 155 resulting from this comparison then undergoes low-pass filtering by the digital low pass filter 125. The digital low-pass filter then generates a 6 bit binary vector, a type of numeric data representing the adjusted gain setting GAINN the VGA 105. In this arrangement, the adjusted gain setting GAINN is synchronously transmitted across a set of signal lines 130 (data lines D0 . . . D5 & clock) to the RF-baseband conversion circuit 100 via decoder 110, which in turn recovers gain compensation information (“COMP” in FIG. 2) necessary to control the VGA 105 based on the received GAINN numeric data. Assuming the VGA 105 has 64 programmable gain settings, 6 bits of numeric data is needed to convey the adjusted gain setting, and so six signal lines 130 D0 . . . D5 plus a CLOCK signal are used to transmit the numeric data in parallel gain amplifier 105. Thus, according to this approach, seven signal lines or traces is required to synchronously convey GAINN numeric data from the baseband processing circuit 150 to the RF-baseband conversion circuit 100. In a limited pinout environment, this represents a relatively wasteful number of dedicated pins (seven on each chip).
As few as two pins on each chip 60, 80 would be required to directly transmit the numeric data using conventional serial transmission techniques. But because of the rapidly changing gain characteristics exhibited by received signals formatted in accordance with the above-mentioned 802.11 standards as well as the processing overhead required, conventional serial transmission of the numeric data is believed to be an unsuitable choice.
Thus, in addition to reducing pinout and circuit traces generally, it would be advantageous if a number of the signal lines 130 needed to convey numeric data could be reduced in order to reduce circuit board 50 real estate and associated pinout requirements for the first and second chips 60, 80. In RF applications such as described above with reference to FIG. 2, reducing the number of necessary circuit board signal traces including signal lines 130 to convey numeric data between chips 60 and 80 is believed to of particular importance here because of their potential for picking up stray RF noise and interference.